Circuit designs that are to be implemented as an integrated circuit (IC) typically are specified using a hardware description language. When implementing an HDL circuit description on a programmable logic device (PLD), the circuit description must undergo several different stages of processing. With respect to a field programmable gate array (FPGA) type of PLD, for example, the circuit design must be mapped onto the FPGA device. That is, circuit elements from the circuit description must be assigned to available components or sites on the target device.
One aspect of mapping is packing different circuit elements into slices. In general, an FPGA includes a large number of configurable logic blocks (CLBs). Each CLB can include a plurality of slices. The different elements of a circuit design, for example, lookup tables (LUTs), flip flops, multiplexers, routing resources, etc., must be assigned to the available slices in the target device.
When packing circuit elements into slices, it is desirable to include elements that are connected together in the circuit design into the same slice. This can reduce wire lengths in the resulting circuit implementation and reduce, if not avoid, routing congestion. Packing circuit elements into slices can be modeled as a clustering problem. Typically, heuristics are used by the implementation tools to determine which circuit elements will be clustered together and placed into a slice.
Once these “clusters” are formed, further analysis must be performed to ensure that each cluster actually fits within a slice. While functions are available within development tools to perform slice validity checking, these tools are complex to develop. Debugging, therefore, also is difficult. Making matters worse, a custom-coded solution must be developed for each different type of slice topology, or architecture, that is made available in a target device.